HBIR (short for HammerBlade IR) is an IR/DSL for continuously reconfigurable polymorphic hardware, specifically the HammerBlade architecture. HBIR expresses the static and dynamic configuration of the target hardware as well as the high-level algorithm to be run. As a DSL, it can express computations resembling traditional multicore programs, systolic data-flow accelerator designs, and vector computations, allowing us to reconfigure hardware based off changing application properties. As an IR, it provides a flexible abstraction level that give higher-level machine learning and graph frameworks a suitable target to compile to.

Lotus is a compiler that parses HBIR programs and targets various hardware instances of HammerBlade. It is currently WIP but will eventually integrate with existing ML and graph compiler stacks and work with a runtime to allow dynamic reconfiguration.

Joint work with Philip Bedoukian and Adrian Sampson. HBIR website.

PSA Backend for P4 Compiler

Like many other areas of computing, networking is moving toward supporting purpose-driven commodity resources in search of a delicate balance of scalability, flexibility, and performance. Analogous within the networking community, a push has begun to explore building network switches that can be programmed to handle network packets in a flexible (e.g., TCP/IPv4, TCP/IPv6, UDP/IPv4, custom protocols, etc.) and performant manner. The P4 language emerged from this effort as a powerful new domain-specific language that gives network engineers the ability to decide how their switches will process network packets programmatically.

Prior to eventual deployment on ASIC hardware, P4 programs can be tested and simulated on software-based network switches which interface with a P4 compiler via interchangeable compiler backends. P4C acts as a reference compiler implementation to target various software-based network switches.

Joint work with Nate Foster. P4C GitHub Repository.